Parallel vs. serial on-chip communication
Proceedings of the 2008 international workshop on System level interconnect prediction
On improving optimization effectiveness in interconnect-driven physical synthesis
Proceedings of the 2009 international symposium on Physical design
Two-phase synchronization with sub-cycle latency
Integration, the VLSI Journal
Asynchronous current mode serial communication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
On each manufactured chip, every wire and via is a little bit different. Most of this variation is accounted for by chip-to-chip, wafer-to-wafer, and lot-to-lot variation. These make chips different from each other, but affect all features on the same chip in the same way. These models predict, for example, that the thickness of a given metal layer may vary considerably, but on a single chip all wires on the same layer are the same thickness. However, there is also on-chip (also called intra-chip, or cross-chip) variation, causing even nominally identical wires and vias on the same chip to differ from each other. This survey looks at some of the physical reasons behind these differences (such as lithography, etching, polishing, alignment, and gradients), how these differences are currently treated by fabs, tools, and designers (in a very ad-hoc manner), and how this topic might be addressed in the future.