Elements of information theory
Elements of information theory
Entropy, counting, and programmable interconnect
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
On partitioning vs. placement rent properties
Proceedings of the 2001 international workshop on System-level interconnect prediction
Multi-terminal nets do change conventional wire length distribution models
Proceedings of the 2001 international workshop on System-level interconnect prediction
Rent's rule based switching requirements
Proceedings of the 2001 international workshop on System-level interconnect prediction
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
Design of FPGA interconnect for multilevel metalization
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Rothko: A Three-Dimensional FPGA
IEEE Design & Test
Placement rent exponent calculation methods, temporal behaviour and FPGA architecture evaluation
Proceedings of the 2003 international workshop on System-level interconnect prediction
Wiring requirement and three-dimensional integration technology for field programmable gate arrays
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
Design of Interconnection Networks for Programmable Logic
Design of Interconnection Networks for Programmable Logic
FPGAs with Multidimensional Switch Topology
IEICE - Transactions on Information and Systems
Designing efficient input interconnect blocks for LUT clusters using counting and entropy
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Designing Efficient Input Interconnect Blocks for LUT Clusters Using Counting and Entropy
ACM Transactions on Reconfigurable Technology and Systems (TRETS) - Special edition on the 15th international symposium on FPGAs
Post-placement interconnect entropy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We introduce the concept of post-placement interconnect entropy: the minimal number of bits required to describe a well-placed netlist, which has connection lengths distributed according to Rent's rule. The entropy is a function of the number N of cells in the netlist and the Rent exponent p. We derive an expression for the entropy per cell and show that it converges as N approaches infinity. The entropy provides an achievable lower bound on the number of configuration bits in a programmable logic device. Specific numerical values are computed for practical situations. For example, any scalable FPGA composed of 4-input lookup table cells would require 31 configuration bits per cell. We compare this to the actual number of configuration bits in a standard FPGA architecture. We generalize the bound to dimensions higher than two, and show that for any p there is an optimal dimension that minimizes the bound.