Principles of digital design
Logic and computer design fundamentals
Logic and computer design fundamentals
RF microelectronics
A Digitally Controlled Shunt Capacitor CMOS Delay Line
Analog Integrated Circuits and Signal Processing - Special issue on selected papers from the 1997 NORCHIP conference
Design of Integrated Circuits for Optical Communications
Design of Integrated Circuits for Optical Communications
A novel delay-locked loop based CMOS clock multiplier
IEEE Transactions on Consumer Electronics
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This paper introduces a low-jitter and wide tuning range delay-locked loop (DLL) -based fractional clock generator (CG) topology. The proposed fractional multiplying DLL (FMDLL) architecture overcomes some disadvantages of phase-locked loops (PLLs) such as jitter accumulation while maintaining the advantageous of a PLL as a multi-rate fractional frequency multiplier. Based on this topology, a CG with 1---2.5 GHz output frequency tuning range has been designed in a digital 0.18 um CMOS technology while the multiplication ratios are M+k/(2NC) in which M, k, and NC are adjustable. To generate some finer ratios, k is changed periodically or randomly (by a digital delta-sigma modulator) between two consecutive integer numbers. Operating in 2.5 GHz, total circuit including digital part consumes 15.5 mW from 1.8 V supply voltage. At the proposed architecture, reference clock is injected into a ring oscillator in specified times and to the specified delay-stages to synthesize the fractional frequency multiplication as well as resetting the accumulated jitter during previous cycles. Operating in maximum speed, simulated RMS (root-mean-square) and PTP (peak-to-peak) jitter values are 1.8 and 14.5 ps, respectively, while the settling time is 5 us.