A fast methodology for first-time-correct design of PLLs using nonlinear phase-domain VCO macromodels

Authors:
Prashant Goyal;Xiaolue Lai;Jaijeet Roychowdhury
Affiliations:
Indian Institute of Technology, Kanpur, India;University of Minnesota, Twin Cities;University of Minnesota, Twin Cities
Venue:
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Year:
2006

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Abstract

We present a novel methodology suitable for fast, correct design of modern PLLs. The central feature of the methodology is its use of accurate, nonlinear behavioral models for the VCO within the PLL, thus removing the need for many time-consuming SPICE-level simulations during the design process. We apply the new methodology to design a novel injection-aided PLL that acquires lock 3 x faster than prior designs, without trading off other design metrics such as jitter. We demonstrate how existing design methodologies based on behavioral simulation are incapable of leading to our new PLL design. The nonlinear behavioral simulations employed in our methodology are about 2 orders of magnitude faster than transistor-level ones, resulting in an overall design productivity gain of an order of magnitude.