IEEE Transactions on Computers
Digital system simulation: methodologies and examples
DAC '98 Proceedings of the 35th annual Design Automation Conference
Cycle and phase accurate DSP modeling and integration for HW/SW co-verification
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A transaction-based unified simulation/emulation architecture for functional verification
Proceedings of the 38th annual Design Automation Conference
Incas: a cycle accurate model of UltraSPARC
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
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As the complexity of SoCs is increasing, hardware/software co-verification becomes an important part of system verification. C-level cycle-based simulation could be an efficient methodology for system verification because of its fast simulation speed. The cycle-based simulation has a limitation in using asynchronous clocks that causes inherent cycle errors. In order to reuse the output of a C-level cycle-based simulation for the verification of a lower level model, the C-level model should be cycle-accurate with respect to the lower level model. In this paper a cycle error correction technique is presented for two asynchronous clock models. An example design is devised to show the effectiveness of the proposed method. Our experimental results show that the fast speed of cycle-based simulation can be fully exploited without sacrificing the cycle accuracy.