An efficient IP-level power model for complex digital circuits

Authors:
Chih-Yang Hsu;Chien-Nan Jimmy Liu;Jing-Yang Jou
Affiliations:
National Chiao Tung University, Hsinchu, Taiwan;National Central University, Taoyuan, Taiwan;National Chiao Tung University, Hsinchu, Taiwan
Venue:
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Year:
2003

Citing 3
Cited 0

Energy characterization based on clustering

DAC '96 Proceedings of the 33rd annual Design Automation Conference
A structure-oriented power modeling technique for macrocells

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power modeling for high-level power estimation

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this paper, we propose an efficient IP-Level power model with a small lookup table for complex CMOS circuits. The table has only one dimension that maps the zero-delay charging and discharging capacitance into the real power consumption of pattern pairs but still has high accuracy. In order to improve the efficiency of the characterization process, the Monte Carlo approach is used during the estimation of the average power to skip the samples that will not increase the accuracy too much. The experimental result shows the table sizes are only up to 107 entries for ISCAS'85 benchmark circuits and the estimation error is only 2.99% on average using the lookup table.