Simulation acceleration of transaction-level models for SoC with RTL sub-blocks

Authors:
Jae-Gon Lee;Wooseung Yang;Young-Su Kwon;Young-Il Kim;Chong-Min Kyung
Affiliations:
Korea Advanced Institute of Science and Technology, Daejeon, Korea;R&D Center, Dynalith Systems Co., Ltd., Daejeon, Korea;R&D Center, Dynalith Systems Co., Ltd., Daejeon, Korea;Korea Advanced Institute of Science and Technology, Daejeon, Korea;Korea Advanced Institute of Science and Technology, Daejeon, Korea
Venue:
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Year:
2005

Citing 3
Cited 1

System Design with SystemC

System Design with SystemC
SystemC: methodologies and applications

SystemC: methodologies and applications
Transaction-Level Models for AMBA Bus Architecture Using SystemC 2.0

DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2

A Prediction Packetizing Scheme for Reducing Channel Traffic in Transaction-Level Hardware/Software Co-Emulation

Proceedings of the conference on Design, Automation and Test in Europe - Volume 1

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper presents an optimized channel usage between simulator and accelerator when the simulator models transaction-level SoC while accelerator models RTL sub-blocks. Conventional simulation accelerators synchronize the progresses of simulator and accelerator at every simulation time, which results in poor performance by splitting transactions on the simulator-to-accelerator channel into pieces. Occasional synchronization with predictions and recoveries makes it possible to merge multiple transfers yielding substantial performance gain compared to the conventional method.