Leakage current cancellation technique for low power switched-capacitor circuits
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
An Access Timing Measurement Unit of Embedded Memory
ATS '02 Proceedings of the 11th Asian Test Symposium
Design Method and Automation of Comparator Generation for Flash A/D Converter
ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
Timing Jitter Measurement of 10 Gbps Bit Clock Signals Using Frequency Division
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Timing measurement unit with multi-stage TVC for embedded memories
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
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A time-to-digital Converter (TDC) circuit is presented to measure the worst-case accumulated jitters over N periods of clock produced by the PLL. Including the most positive jitter and the most negative jitter, the worst case jitters can be calculated through the proposed approach. In a case-study, by applying the proposed. TDC circuit with 4-bit flash ADC and the accumulated period N=8, the frequency range of the measured signal, resolution and linearity error are 0.7-1.4GHz, 44ps and 1.25%, respectively. Using a 0.25um 1P6M CMOS process, the HSPICE simulation result shows that the maximum measurement error is 1 LSB after calibration.