Analysis and Design of Analog Integrated Circuits
Analysis and Design of Analog Integrated Circuits
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The V-NPN transistor in deep n-well CMOS process has small flicker noise. The proposed three-stage operational amplifier uses parallel connection V-NPN as input differential pair for low noise. However, the only significant disadvantage of V-NPN transistor as compared to MOSFET transistor is input bias current, which will result in input current noise. For overcoming this effect, a novel input bias current cancellation circuit has been proposed in this work for high precision. The proposed operational amplifier has combined low noise and high precision performance. Good noise performance 2.04nV/ at baseband has been achieved, and flicker noise corner frequency is about 1.78KHz. Moreover input bias current is almost negligible. The relatively high operating current of the input stage reduces voltage noise and increases gain bandwidth. 1.6GHz gain bandwidth with 68-degree phase margin is adequate for high frequency analog application.