Allowing for ILP in an embedded Java processor
Proceedings of the 27th annual international symposium on Computer architecture
Java Virtual Machine Specification
Java Virtual Machine Specification
On the design of the local variable cache in a hardware translation-based java virtual machine
LCTES '05 Proceedings of the 2005 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Java type confusion and fault attacks
FDTC'06 Proceedings of the Third international conference on Fault Diagnosis and Tolerance in Cryptography
Java bytecode to hardware made easy with bluespec system verilog
Proceedings of the 10th International Workshop on Java Technologies for Real-time and Embedded Systems
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Bytecode hardware-translation improves the performance of a Java Virtual Machine (JVM) with small hardware resource and complexity overhead. Instruction folding is a technique to further improve the performance of a JVM by reducing the redundancy in the stack-based instruction execution. However, the variable instruction length of the Java bytecode makes the folding logic complex. In this paper, we propose a folding scheme with reduced hardware complexity and evaluate its performance. For seven benchmark cases, the proposed scheme folded 6.6% to 37.1% of the bytecodes which correspond to 84.2% to 102% of the PicoJava-II's performance.