A characterization of speech recognition on modern computer systems

Authors:
K. Agaram;S. W. Keckler;D. Burger
Affiliations:
Dept. of Comput. Sci., Texas Univ., Austin, TX, USA;Dept. of Comput. Sci., Texas Univ., Austin, TX, USA;Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
Venue:
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
Year:
2001

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Abstract

In this paper we describe and characterize the speech recognition process, and assess the suitability of current microprocessors and memory systems for running speech recognition applications. We use representative benchmark applications-RASTA to characterize the signal-processing on the front end, and SPHINX for the graph search on the back end Recognition time is dominated by the back end, which substantially exercises the memory system and exhibits low levels of instruction-level parallelism (ILP). As a result, SPHINX yields an average instructions per cycle (IPC) of 0.64 on a simulated 4-issue out-of-order microprocessor We identify intelligent layout and thread-level parallelization as the primary methods to improve throughput, showing tipper bounds on the performance improvements that these methods can achieve.