Optimized Design of Interconnected Bus on Chip for Low Power

Authors:
Donghai Li;Guangsheng Ma;Gang Feng
Affiliations:
Harbin Engineering University, China;Harbin Engineering University, China;Harbin Engineering University, China
Venue:
IMSCCS '06 Proceedings of the First International Multi-Symposiums on Computer and Computational Sciences - Volume 2 (IMSCCS'06) - Volume 02
Year:
2006

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On-Chip Communication Architectures: System on Chip Interconnect

On-Chip Communication Architectures: System on Chip Interconnect

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Abstract

In this paper, we firstly propose an on-chip bus power consumption model, which includes the self transition power dissipated on the signal lines and the coupled transition power dissipated between every two signal lines. And then a new heuristic algorithm is proposed to determine a physical order of signal lines in bus. Experimental results show that average power saving 26.85%.