Active messages: a mechanism for integrated communication and computation
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
U-Net: a user-level network interface for parallel and distributed computing
SOSP '95 Proceedings of the fifteenth ACM symposium on Operating systems principles
An implementation and analysis of the virtual interface architecture
SC '98 Proceedings of the 1998 ACM/IEEE conference on Supercomputing
IEEE Standard for Scalable Coherent Interface, Science: IEEE Std. 1596-1992
IEEE Standard for Scalable Coherent Interface, Science: IEEE Std. 1596-1992
Journal of Parallel and Distributed Computing - Special issue on cluster and network-based computing
Virtual-Memory-Mapped Network Interfaces
IEEE Micro
VIBe: A Micro-benchmark Suite for Evaluating Virtual Interface Architecture (VIA) Implementations
IPDPS '01 Proceedings of the 15th International Parallel & Distributed Processing Symposium
CANPC '00 Proceedings of the 4th International Workshop on Network-Based Parallel Computing: Communication, Architecture, and Applications
Efficient Virtual Interface Architecture (VIA) Support for the IBM SP Switch-Connected NT Clusters
IPDPS '00 Proceedings of the 14th International Symposium on Parallel and Distributed Processing
Application performance on the Direct Access File System
WOSP '04 Proceedings of the 4th international workshop on Software and performance
High Performance Messaging on Workstations: Illinois Fast Messages (FM) for Myrinet
Supercomputing '95 Proceedings of the 1995 ACM/IEEE conference on Supercomputing
ALS'00 Proceedings of the 4th annual Linux Showcase & Conference - Volume 4
High-performance ethernet-based communications for future multi-core processors
Proceedings of the 2007 ACM/IEEE conference on Supercomputing
HPCC'06 Proceedings of the Second international conference on High Performance Computing and Communications
| Hi-index | 0.00 |
This paper presents the implementation and performance of a hardware-VIA-based network adapter on Gigabit Ethernet. VIA is a useer-level communication interface for high performance PC clustering. The network adapter is a 64-bit/66 MHz PCI plug-in card containing an FPGA for the VIA Protocol Engine and a Gigabit Ethernet chip to construct a high performance system area network. The network adapter performs virtual-to-physical address translation, doorbell, RDMA write, and send/receive completion operations in hardware without kernel intervention. In particular, the Address Translation Table (ATT) is stored on the local memory of the network adapter, and the VIA Protocol Engine efficiently controls the address translation process by directly accessing the ATT. In addition, Address Prefetch Buffer is used to reduce the time of address translation process in the receiver. As a result, the communication overhead during send/receive transactions is greatly reduced. Our experimental results show a minimum latency of 8.2 µs, and a maximum bandwidth of 112.1 MB/s. In terms of minimum latency, the hardware-VIA-based network adapter performs 2.8 times and 3.3 times faster than M-VIA, which is a software implementation of VIA, and TCP/IP, respectively, over Gigabit Ethernet. In addition, the maximum bandwidth of the hardware-VIA-based network adapter is 24% and 55% higher than M-VIA and TCP/IP, respectively. These results show that the performance of HVIA-GE is far better than that of ServerNet II, which is a hardware version of VIA developed by Tandem/Compaq.