Proceedings of the DIMACS/SYCON workshop on Hybrid systems III : verification and control: verification and control
Visual modeling with Rational Rose and UML
Visual modeling with Rational Rose and UML
A Comparison of Statecharts Variants
ProCoS Proceedings of the Third International Symposium Organized Jointly with the Working Group Provably Correct Systems on Formal Techniques in Real-Time and Fault-Tolerant Systems
Model-Checking for Real-Time Systems
FCT '95 Proceedings of the 10th International Symposium on Fundamentals of Computation Theory
PVS: A Prototype Verification System
CADE-11 Proceedings of the 11th International Conference on Automated Deduction: Automated Deduction
Embedding UML and Type Theory to Formalize the Process of Requirement Engineering
TOOLS '00 Proceedings of the 36th International Conference on Technology of Object-Oriented Languages and Systems (TOOLS-Asia'00)
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This chapter uses the Unified Modeling Language (UML) and the theorem prover PVS to formalize and analyze a part of the BART/AATC system. Our approach to the formalization and analysis takes five steps within which we iterate a number of activities, both for constructing and validating UML diagrams of the system. We find inconsistencies and omissions in the informal requirements specification and produce a formal specification which we can use for further system design. A simple UML model of the behavior of the train is created, and a controller is designed and proven to be correct within that model.