Building the functional performance model of a processor

Authors:
Alexey Lastovetsky;Ravi Reddy;Robert Higgins
Affiliations:
University College Dublin, Belfield, Ireland;University College Dublin, Belfield, Ireland;University College Dublin, Belfield, Ireland
Venue:
Proceedings of the 2006 ACM symposium on Applied computing
Year:
2006

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Abstract

In this paper, we present an efficient procedure for building a piecewise linear function approximation of the speed function of a processor with hierarchical memory structure. The procedure tries to minimize the experimental time used for building the speed function approximation. We demonstrate the efficiency of our procedure by performing experiments with a matrix multiplication application and a Cholesky Factorization application that use memory hierarchy efficiently and a matrix multiplication application that uses memory hierarchy inefficiently on a local network of heterogeneous computers.