An efficient LDPC code structure combined with the concept of difference family

  • Authors:

  • Yuan-Jih Chu;Sau-Gee Chen

  • Affiliations:

  • National Chiao Tung University, Hsinchu, Taiwan, ROC;National Chiao Tung University, Hsinchu, Taiwan, ROC

  • Venue:
  • Proceedings of the 2006 international conference on Wireless communications and mobile computing
  • Year:
  • 2006

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Abstract

In this paper, we construct a new irregular LDPC code structure combined with a concept of difference family [5]. The corresponding decoders for the proposed LDPC code structure achieve better performance than those decoders for random-structured codes and the quasi-cyclic codes, when simulated with the commonly used sum-product iterative decoding algorithm and the min-sum based algorithms. Meanwhile the resulting codes have both low encoding and decoding complexities comparable to those of the efficient quasi-cycle LDPC codes. Specifically, we propose a new code structure for parity-check matrices and devise new sets of the difference families for the new matrices. An LDPC decoder based on the proposed code structure has been realized with UMC 0.18 μm ASIC process technology. The decoder assumes a code rate of 3/4, a code length of 960 bits, with maximum 10 decoding iterations. The decoder can achieve a decoding throughput rate up to 370Mbps and take an area of 800k gates.