Content-addressable memory core cells: a survey
Integration, the VLSI Journal
Fast Updating Algorithms for TCAMs
IEEE Micro
Reducing TCAM Power Consumption and Increasing Throughput
HOTI '02 Proceedings of the 10th Symposium on High Performance Interconnects HOT Interconnects
Use of selective precharge for low-power on the match lines of content-addressable memories
MTDT '97 Proceedings of the 1997 IEEE International Workshop on Memory Technology, Design and Testing
Packet Classification Using Extended TCAMs
ICNP '03 Proceedings of the 11th IEEE International Conference on Network Protocols
Front end device for content networking
Proceedings of the conference on Design, automation and test in Europe
A Hybrid IP Forwarding Engine with High Performance and Low Power
ICCSA '09 Proceedings of the International Conference on Computational Science and Its Applications: Part II
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Stringent memory access and search speed requirements are two of the main bottlenecks in wire speed processing. Most viable search engines are implemented in content addressable memories (CAMs). CAMs have high operational speed advantage over other memory search algorithms. However, this performance advantage comes with a price of higher silicon area, and higher power consumption. Ternary CAMs (TCAM) are widely used for route lookup operations in networking applications. IP address prefix length distribution in the core routers shows a similar characteristic such that the prefixes with 24 or longer bits attract more than 50% of the traffic. Based on this statistical observation, we propose a TCAM architecture that can be used on top of the previously reported power saving techniques and it offers additional 30% reduction in power consumption. Furthermore, we model the dynamic power consumption in TCAM circuits due match, mismatch and don't care activities.