Modeling and Verification of Time Dependent Systems Using Time Petri Nets
IEEE Transactions on Software Engineering
A high-performance architecture with a macroblock-level-pipeline for MPEG-2 coding
Real-Time Imaging - Special issue on special purpose architectures for real-time imaging
Synthesis of a Class of Deadlock-Free Petri Nets
Journal of the ACM (JACM)
Guaranteeing Real-Time Requirements With Resource-Based Calibration of Periodic Processes
IEEE Transactions on Software Engineering
Embedded System Design Framework for Minimizing Code Size and Guaranteeing Real-Time Requirements
RTSS '02 Proceedings of the 23rd IEEE Real-Time Systems Symposium
Extensible and Scalable Time Triggered Scheduling
ACSD '05 Proceedings of the Fifth International Conference on Application of Concurrency to System Design
Structural Translation from Time Petri Nets to Timed Automata
Electronic Notes in Theoretical Computer Science (ENTCS)
Architecture and bus-arbitration schemes for MPEG-2 video decoder
IEEE Transactions on Circuits and Systems for Video Technology
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In designing bus based systems with parallel and pipelined architecture, it is important to derive a real time budget (a specified execution time limit) for each task of a bus based system while satisfying given end-to-end real-time constraints of the entire system such as throughput and latency constraints. In this paper, we define a bus scenario representing a set of possible execution sequences of tasks and bus transfers executed in a bus based system. Then we propose a method for deriving real time budgets of all the tasks running in parallel and pipelined fashion from the pair of a system configuration (such as bus topology) and a bus scenario. In deriving such real time budgets, we consider computational complexity of each task, the amount of bus transfers and bus arbitration policies(e.g. fixed priority or time divided round robin based arbitration). We show that the proposed method is effective for designing several bus based systems such as MPEG decoders.