A multithreaded PowerPC processor for commercial servers
IBM Journal of Research and Development
POWER4 system microarchitecture
IBM Journal of Research and Development
Proceedings of the 33rd annual international symposium on Computer Architecture
SPEC CPU2006 sensitivity to memory page sizes
ACM SIGARCH Computer Architecture News
End-to-end performance of commercial applications in the face of changing hardware
ACM SIGOPS Operating Systems Review
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The POWER5TM system incorporates several features designed to improve performance by eliminating bottlenecks and accelerating common functions used in operating systems. This paper discusses how two of the supported operating systems for POWER5--AIX® and LinuxTM--make use of these features to deliver improved system scalability and performance. In particular, the overheads for synchronizing translation-lookaside buffer (TLB) invalidations between processors, and for ensuring that the instruction cache is kept coherent by software, have been removed. The POWER5 simultaneous multithreading (SMT) implementation has features which allow operating systems to optimize the system for the kinds of applications being executed. We discuss how the operating systems approach the problems of scheduling tasks across the system, of determining when to switch processors between single-threaded (ST) and SMT mode, and of accounting accurately for CPU usage when in the SMT mode.