FPGA architecture for static background subtraction in real time

Authors:
Jozias Oliveira;André Printes;R. C. S Freire;Elmar Melcher;Ivan S. S. Silva
Affiliations:
Genius Institute of Technology, Manaus, AM, Brasil;Genius Institute of Technology, Manaus, AM, Brasil;Federal University of Campina Grande, Campina Grande, PB, Brasil;Federal University of Campina Grande, Campina Grande, PB, Brasil;Federal University of Pará, Belém, PA, Brasil
Venue:
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
Year:
2006

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Abstract

Background subtraction is a method typically used to segment moving regions in image sequences taken from a static camera by comparing each new frame to a model of the scene background. In this paper, we present an FPGA architecture for background subtraction, taking advantage of the data and logical parallel opportunities offered by a field programmable gate array (FPGA) architecture. At a clock rate of 40 MHz, the architecture can process 30 frames per second, where the image resolution is 240 x 120. The capability of the system is demonstrated for several tests and video sequences.