An FPGA-Based Verification Framework for Real-Time Vision Systems

  • Authors:

  • Gooitzen van der Wal;Frederic Brehm;Michael Piacentino;James Marakowitz;Eduardo Gudis;Azhar Sufi;James Montante

  • Affiliations:

  • Embedded Vision Systems Sarnoff Corporation Princeton, NJ;Embedded Vision Systems Sarnoff Corporation Princeton, NJ;Embedded Vision Systems Sarnoff Corporation Princeton, NJ;Embedded Vision Systems Sarnoff Corporation Princeton, NJ;Embedded Vision Systems Sarnoff Corporation Princeton, NJ;Embedded Vision Systems Sarnoff Corporation Princeton, NJ;Embedded Vision Systems Sarnoff Corporation Princeton, NJ

  • Venue:
  • CVPRW '06 Proceedings of the 2006 Conference on Computer Vision and Pattern Recognition Workshop
  • Year:
  • 2006

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Abstract

Field-Programmable Gate Arrays (FPGAs) have become a mainstay in the digital electronics world both for the ease of implementation as well as their inherent usefulness in incrementally refining hardware designs. When moving to an Application Specific Integrated Circuit (ASIC) or System on a Chip (SoC), verification becomes a very time consuming process, with virtually no room for error. As a result, a variety of methods have been devised to decrease the risk when creating an ASIC or SoC. We describe a hardware and software framework for testing real-time vision algorithms for lowering the uncertainty in FPGA and SoC development, while reducing the SoC verification time. The framework benefits from hardware and software verification, ease of reconfiguration for testing multiple vision algorithms, and an iterative hardware/ software co-design.