Regular interactive algorithms and their implementations on processor arrays
Regular interactive algorithms and their implementations on processor arrays
Elements of the Theory of Computation
Elements of the Theory of Computation
The VLSI Design Automation Assistant: Prototype system
DAC '83 Proceedings of the 20th Design Automation Conference
Automatic synthesis of systolic arrays from uniform recurrent equations
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
High-level Optimization in a Silicon Compiler
High-level Optimization in a Silicon Compiler
Synthesis of digital designs from recursion equations
Synthesis of digital designs from recursion equations
Automated synthesis of data paths in digital systems (design space)
Automated synthesis of data paths in digital systems (design space)
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The major drawback of reported high level synthesis techniques is their limited applicability to a specific class of algorithms without extendibility to general algorithms and the lack of a formal approach to prove the correctness of the such techniques. In this paper, we introduce a novel approach for high level synthesis from &mgr;-recursive algorithms. Two features are provided by the approach: completeness and correctness. Completeness means the ability to use the approach for any general algorithm. Correctness is achieved by using a set of transformations that are proved to be correct. A formal framework for the synthesis procedure has been developed which can be easily automated. A given algorithm will be represented in a new developed language termed Algorithm Specification Language (ASL). ASL has the ability to describe any general algorithm. An automatic procedure is used to transform an ASL representation into a specific realization specification using a correctness preserving set of transformations. The realization format is based on representing the digital architectures by a Realization Specification Language(RSL).