Fault Tolerant System Design Method Based on Self-Checking Circuits

  • Authors:

  • Pavel Kubalik;Petr Fiser;Hana Kubatova

  • Affiliations:

  • Czech Technical University in Prague, Czech Republic;Czech Technical University in Prague, Czech Republic;Czech Technical University in Prague, Czech Republic

  • Venue:
  • IOLTS '06 Proceedings of the 12th IEEE International Symposium on On-Line Testing
  • Year:
  • 2006

Quantified Score

Hi-index 0.00

Visualization

Abstract

This paper describes a highly reliable digital circuit design method based on totally self checking blocks implemented in FPGAs. The bases of the self checking blocks are parity predictors. The parity predictor design method based on multiple parity groups is proposed. Proper parity groups are chosen in order to obtain minimal area overhead and to decrease the number of undetectable faults.