The iAPX 286 protection architecture

  • Authors:
  • Jack Klebanoff

  • Affiliations:
  • Intel Corp., Santa Clara, CA

  • Venue:
  • ACM SIGSMALL Newsletter
  • Year:
  • 1983

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Abstract

The iAPX 286 is a 16 bit microprocessor introduced by Intel in 1982. Its main features are as follows.1) High performance, 2 to 3 times the performance of the Intel 8086 at equivalent clock speeds.2) A protection architecture that is capable of supporting secure and reliable systems.3) A high performance memory management and protection mechanism (high performance is retained when memory management and protection is turned on).4) Compatibility with the Intel 8086/8088.This article will give an overview of the protection architecture of the Intel iAPX 286.With current software technology, it is not feasible to implement large, or even medium sized, software systems that are completely correct. Generally the number of bugs increases at least linearly with the software size. If a system is to show some robustness its most crucial sections must be protected from less crucial sections. If enforcement of a security policy is the key measure of robustness, then the part of the operating system that enforces security must be small and protected from the rest of the system. Yet one does not want to throw the bulk of the operating system to the wolves; it should be protected from application software.One quickly comes to the conclusion that a traditional two level, user/supervisor, protection architecture is not adequate for supporting secure, high performance, systems. Instead, a Multics-like ring architecture [1] was chosen for the iAPX 286.