Design method for CMOS current-source modes power amplifiers based on PAE optimization

  • Authors:
  • N. Dehaese;S. Bourdel;J. Gaubert;Y. Bachelet;H. Barthélemy

  • Affiliations:
  • L2MP UMR CNRS 6137 Polytech'Marseille, IMT Technopôle de Château Gombert, France 13451;L2MP UMR CNRS 6137 Polytech'Marseille, IMT Technopôle de Château Gombert, France 13451;L2MP UMR CNRS 6137 Polytech'Marseille, IMT Technopôle de Château Gombert, France 13451;L2MP UMR CNRS 6137 Polytech'Marseille, IMT Technopôle de Château Gombert, France 13451;L2MP UMR CNRS 6137 Polytech'Marseille, IMT Technopôle de Château Gombert, France 13451

  • Venue:
  • Analog Integrated Circuits and Signal Processing
  • Year:
  • 2006

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Abstract

An efficient method for CMOS current-source modes (A, B, AB, C classes) Power Amplifier (PA) design for low-power applications is presented. This method allows to set the conduction angle 驴 and the transistor size W/L in order to maximize the PAE. In a first step, an analytical approach, built from a simple transistor model, gives a first approximation of the optimum 驴 and W/L. In a second step and from the analytical results, a simulation approach, illustrated with a 0.28驴m CMOS foundry design-kit, allows to precisely determine the optimum conduction angle and the transistor size. A PA designed with this method at 2.45 GHz for a class 2 Bluetooth application shows a 41% PAE and a surface consumption of 0.28 mm2 for an output power of 4 dBm.