Fast Bit Compression and Expansion with Parallel Extract and Parallel Deposit Instructions

  • Authors:

  • Yedidya Hilewitz;Ruby B. Lee

  • Affiliations:

  • Princeton University, Princeton, NJ;Princeton University, Princeton, NJ

  • Venue:
  • ASAP '06 Proceedings of the IEEE 17th International Conference on Application-specific Systems, Architectures and Processors
  • Year:
  • 2006

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Abstract

Current microprocessor instruction set architectures are word oriented, with some subword support. Many important applications, however, can realize substantial performance benefits from bitoriented instructions. We propose the parallel extract (pex) and parallel deposit (pdep) instructions to accelerate compressing and expanding selections of bits. We show that these instructions can be implemented by the fast inverse butterfly and butterfly network circuits. We evaluate latency and area costs of alternative functional units for implementing subsets of advanced bit manipulation instructions. We show applications exhibiting significant speedup, 3.41脳 on average over a basic RISC architecture, and 2.48脳 on average over an instruction set architecture (ISA) that supports extract and deposit instructions.