Application-specific Processor Architecture: Then and Now
Journal of Signal Processing Systems
A pattern based instruction encoding technique for high performance architectures
International Journal of High Performance Systems Architecture
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This work proposes a new architecture and execution model called 2D-VLIW. This architecture adopts an execution model based on large pieces of computation running over a matrix of functional units connected by a set of local register spread across the matrix. Experiments using the Mediabench and SPECint00 programs and the Trimaran compiler show performance gains ranging from 5% to 63%, when comparing our proposal to an EPIC architecture with the same number of registers and functional units. We also show that the g721-enc program running on a 2D-VLIW 3脳3 matrix had a speedup of 1.37 over a 2脳2 matrix while the same program over the EPIC processor with 9 functional units had a speedup of 1.12 over an EPIC processor with 4 functional units. For some internal procedures from Mediabench and SPECint programs, the average 2D-VLIW OPC (operations per cycle) was up to 10 times greater than for the equivalent EPIC processor.