Low Complexity Design of High Speed Parallel Decision Feedback Equalizers

Authors:
Daesun Oh;Keshab K. Parhi
Affiliations:
University of Minnesota, Minneapolis, MN;University of Minnesota, Minneapolis, MN
Venue:
ASAP '06 Proceedings of the IEEE 17th International Conference on Application-specific Systems, Architectures and Processors
Year:
2006

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A low-complexity decision feedforward equalizer architecture for high-speed receivers on highly dispersive channels

Journal of Control Science and Engineering - Special issue on Hardware Implementation of Digital Signal Processing Algorithms

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Abstract

This paper proposes a novel parallel approach for pipelining of nested multiplexer loops to design high speed decision feedback equalizers (DFEs) based on look-ahead techniques. It is well known that the DFE is an efficient scheme to suppress intersymbol interference (ISI) in various communication and magnetic recording systems. However, the feedback loop within a DFE limits an upper bound of the achievable high speed in hardware implementation. A straightforward parallel implementation requires more hardware complexity. The novel proposed technique offers significant reduction of hardware complexity of 56% and 80% over the conventional parallel six-tap DFE architectures for 10 Gbps and 20 Gbps throughput, respectively.