Open Source High Performance Floating-Point Modules

Authors:
K. Scott Hemmert;Keith D. Underwood
Affiliations:
Sandia National Laboratories;Sandia National Laboratories
Venue:
FCCM '06 Proceedings of the 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Year:
2006

Citing 0
Cited 4

Architectural modifications to enhance the floating-point performance of FPGAs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reconfiguration and Communication-Aware Task Scheduling for High-Performance Reconfigurable Computing

ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Improving Floating-Point Performance in Less Area: Fractured Floating Point Units (FFPUs)

Journal of Signal Processing Systems
Area-efficient architectures for double precision multiplier on FPGA, with run-time-reconfigurable dual single precision support

Microelectronics Journal

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Abstract

Given the logic density of modern FPGAs, it is feasible to use FPGAs for floating-point applications. However, it is important that any floating-point units that are used be highly optimized. This paper introduces an open source library of highly optimized floating-point units for Xilinx FPGAs. The units are fully IEEE compliant and acheive approximately 230 MHz operation frequency for doubleprecision add and multiply in a Xilinx Virtex-2-Pro FPGA (-7 speed grade). This speed is acheived with a 10 stage adder pipeline and a 12 stage multiplier pipeline. The area requirement is 571 slices for the adder and 905 slices for the multiplier.