A Reconfigurable Cluster-on-Chip Architecture with MPI Communication Layer

Authors:
J. A. Williams;I. Syed;J. Wu;N. W. Bergmann
Affiliations:
University of Queensland, Brisbane, Australia;University of Queensland, Brisbane, Australia;University of Queensland, Brisbane, Australia;University of Queensland, Brisbane, Australia
Venue:
FCCM '06 Proceedings of the 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Year:
2006

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Adaptive communication mechanism for accelerating MPI functions in NoC-based multicore processors

ACM Transactions on Architecture and Code Optimization (TACO)

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Abstract

We present a reconfigurable cluster-on-chip architecture and supporting parallel programming software library based on the well-known Message Passing Interface (MPI) standard. The intent is to allow designers to program multi-core reconfigurable systems on chip using the same or similar methodologies that yielded tremendous productivity improvements in the workstation and HPC cluster community. Additionally the architecture is designed to support native hardware processing modules to participate in the MPI network as fully-fledged peers.