Scheduling divisible loads on partially reconfigurable hardware

Authors:
K. N. Vikram;V. Vasudevan
Affiliations:
Indian Institute of Technology Madras, Chennai, India;Indian Institute of Technology Madras, Chennai, India
Venue:
FCCM '06 Proceedings of the 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Year:
2006

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Mapping data-parallel tasks onto partially reconfigurable hybrid processor architectures

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

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Abstract

For a task mapped to the reconfigurable fabric (RF) of a partially reconfigurable hybrid processor architecture, significant speedup can be obtained if multiple processing units (PUs) are used to accelerate the task. In this paper, we present the results obtained from a quantitative analysis for a single data-parallel task mapped to the RF of a busbased hybrid processor architecture. The architectural constraints in this case include run-time reconfiguration delay and a shared data bus to main memory.