A versatile architecture for VLSI implementation of the Viterbi algorithm

Authors:
B. K. Min;N. Demassieux
Affiliations:
Telecom Paris Univ., France;Telecom Paris Univ., France
Venue:
ICASSP '91 Proceedings of the Acoustics, Speech, and Signal Processing, 1991. ICASSP-91., 1991 International Conference
Year:
1991

Citing 0
Cited 2

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Design of a 20-Mb/s 256-state viterbi decoder

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Abstract

The proposed architecture consists of a novel mapping of the shuffle-exchange network for metric updating. This architecture has been shown to provide practical layouts in VLSI implementation. It can be adjustable to the various performance levels of throughput by exploiting the inherent parallelism of the Viterbi algorithm to varying degrees. This preservation of structural uniformity when trading the throughput for area makes the architecture very versatile, thus giving the designer a broad spectrum of alternatives, and additionally providing a systematic guideline to optimize the design for any specific area-time tradeoff requirement.