Rate-optimal DSP synthesis by pipeline and minimum unfolding
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The authors propose a systematic approach to a rate-optimal, fully static multiprocessor implementation for a real-time recurrence algorithm. The objective is to minimize the number of processors and the number of interprocessor communication links. For any arbitrary algorithm, rate optimal fully static implementation may not be obtained without algorithm transformation. The authors generalize the perfect-rate graphs, which can always achieve their rate-optimal fully static implementations, requiring no algorithm transformation, by relaxing the restriction stated by K. K. Parki and D. G. Messerschmitt (1989). An optimal unfolding factor is introduced to tell at least how many times to unfold a loop to its corresponding generalized perfect-rate graph. A scheme employing the artificial-intelligence planning problem solver is proposed to do scheduling and processor assignment for a generalized perfect-rate graph so that the design can meet the goal.