Dynamic instruction scheduling in a trace-based multi-threaded architecture
International Journal of Parallel Programming
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A multi-threaded, dynamically trace-based architecture is presented, designed to make fuller usage of the PEs of a VLIW. The mDTSVLIW extends our single process DTSVLIW design to reduce the effect of both horizontal and vertical waste, and of variable latencies. The DTSVLIW performs single instruction execution of a process, dynamically scheduling these in hardware into blocks of VLIW instructions for VLIW execution. The mDTSVLIW maintains these features and adds simultaneous multithreading by issuing and executing instructions from VLIW blocks from several threads. Preliminary experiments to explore the design varied the number of threads, scalar processors and cache sizes. Results achieve PE utilization of up to 87% on a 4-thread, 1- scalar, 8 PE design, with speed-ups of up to 6.3 that of a single processor. Noticeably it only needs a single scalar process to be scheduled at any time, with main memory fetches being 1-4% that of a single processor.