Monitoring tools for multiprocessors
Microprocessing and Microprogramming
Debug system targets multiprocessor design
Computer Design
Hardware-Assisted Multiprocessor Performance Measurement
Performance '87 Proceedings of the 12th IFIP WG 7.3 International Symposium on Computer Performance Modelling, Measurement and Evaluation
MIDAS: Integrated Design and Simulation of Distributed Systems
IEEE Transactions on Software Engineering
Monitoring program behaviour on SUPRENUM
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
Dynamic control of performance monitoring on large scale parallel systems
ICS '93 Proceedings of the 7th international conference on Supercomputing
The SHRIMP performance monitor: design and applications
SPDT '96 Proceedings of the SIGMETRICS symposium on Parallel and distributed tools
Performance analysis using the MIPS R10000 performance counters
Supercomputing '96 Proceedings of the 1996 ACM/IEEE conference on Supercomputing
In Search of a Standards-Based Approach to Hybrid Performance Monitoring
IEEE Parallel & Distributed Technology: Systems & Technology
IEEE Design & Test
Distributed Performance Monitoring: Methods, Tools, and Applications
IEEE Transactions on Parallel and Distributed Systems
A scalable performance analysis tool for PowerPC based MPP systems
PAS '95 Proceedings of the First Aizu International Symposium on Parallel Algorithms/Architecture Synthesis
Fault Injection Based on a Partial View of the Global State of a Distributed System
SRDS '99 Proceedings of the 18th IEEE Symposium on Reliable Distributed Systems
A performance methodology for commercial servers
IBM Journal of Research and Development
| Hi-index | 4.10 |
Performance measurement for loosely and tightly coupled multiple-instruction multiple-data multiprocessor systems is addressed. For the paradigm of multiple processors solving a single problem faster, a taxonomy of hardware-supported measurement approaches is presented and critiqued. A hybrid measurement system that is, software with hardware support, is presented. The system, called the trace measurement system (Trams), initially consisted of a memory-mapped device using software triggering and hardware sampling of time and processor identification. A VLSI chip set that integrates the Trams functions of software triggering and hardware sampling with hardware counters is described, and its application is discussed. The tool introduces little perturbation and provides physically small and affordable performance-measurement support.