Navigating Register Placement for Low Power Clock Network Design*This work was supported by Hi-Tech Research & Development (863) Program of China 2002AA1Z1460, the National Natural Science Foundation of China (NSFC) 60476014, Specialized Research Fund for the Doctoral Program of Higher Education: SRFDP-20020003008 and DAC Graduate Scholarship. Some preliminary results of this paper was presented at Asia South Pacific Design Automation Conference (ASPDAC), January, 2005 [17].

  • Authors:

  • Yongqiang Lu;Chin-Ngai Sze;Xianlong Hong;Qiang Zhou;Yici Cai;Liang Huang;Jiang Hu

  • Affiliations:

  • The authors are with the Department of Computer Science and Technology, Tsinghua University, Beijing 100084, P.R.C. E-mail: luyj01@mails.tsinghua.edu.cn,;The authors are with the Department of Electrical Engineering, Texas A&M University, College Station, TX 77843, U.S.A.;The authors are with the Department of Computer Science and Technology, Tsinghua University, Beijing 100084, P.R.C. E-mail: luyj01@mails.tsinghua.edu.cn,;The authors are with the Department of Computer Science and Technology, Tsinghua University, Beijing 100084, P.R.C. E-mail: luyj01@mails.tsinghua.edu.cn,;The authors are with the Department of Computer Science and Technology, Tsinghua University, Beijing 100084, P.R.C. E-mail: luyj01@mails.tsinghua.edu.cn,;The authors are with the Department of Computer Science and Technology, Tsinghua University, Beijing 100084, P.R.C. E-mail: luyj01@mails.tsinghua.edu.cn,;The authors are with the Department of Electrical Engineering, Texas A&M University, College Station, TX 77843, U.S.A.

  • Venue:
  • IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
  • Year:
  • 2005

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Abstract

With VLSI design development, the increasingly severe power problem requests to minimize clock routing wirelength so that both power consumption and power supply noise can be alleviated. In contrast to most of traditional works that handle this problem only in clock routing, we propose to navigate standard cell register placement to locations that enable further less clock routing wirelength and power. To minimize adverse impacts to conventional cell placement goals such as signal net wirelength and critical path delay, the register placement is carried out in the context of a quadratic placement. The proposed technique is particularly effective for the recently popular prescribed skew clock routing. Experiments on benchmark circuits show encouraging results.