Quality and Power Efficient Architecture for the Discrete Cosine Transform

  • Authors:

  • Chi-Chia Sung;Shanq-Jang Ruan;Bo-Yao Lin;Mon-Chau Shie

  • Affiliations:

  • The authors are with the Department of Electronic Engineering, National Taiwan University of Science and Technology, Taipei 106, Taiwan. E-mail: M9302107@mail.ntust.edu.tw, E-mail: sjruan@et.ntust ...;The authors are with the Department of Electronic Engineering, National Taiwan University of Science and Technology, Taipei 106, Taiwan. E-mail: M9302107@mail.ntust.edu.tw, E-mail: sjruan@et.ntust ...;The authors are with the Department of Electronic Engineering, National Taiwan University of Science and Technology, Taipei 106, Taiwan. E-mail: M9302107@mail.ntust.edu.tw, E-mail: sjruan@et.ntust ...;The authors are with the Department of Electronic Engineering, National Taiwan University of Science and Technology, Taipei 106, Taiwan. E-mail: M9302107@mail.ntust.edu.tw, E-mail: sjruan@et.ntust ...

  • Venue:
  • IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
  • Year:
  • 2005

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Abstract

In recent years, the demand for multimedia mobile battery-operated devices has created a need for low power implementation of video compression. Many compression standards require the discrete cosine transform (DCT) function to perform image/video compression. For this reason, low power DCT design has become more and more important in today's image/video processing. This paper presents a new power-efficient Hybrid DCT architecture which combines Loeffler DCT and binDCT in terms of special property on luminance and chrominance difference. We use Synopsys PrimePower to estimate the power consumption in a TSMC 0.25-μm technology. Besides, we also adopt a novel quality assessment method based on structural distortion measurement to measure the quality instead of peak signal to noise rations (PSNR) and mean squared error (MSE). It is concluded that our Hybrid DCT offers similar quality performance to the Loeffler, and leads to 25% power consumption and 27% chip area savings.