Efficient algorithm and architecture of critical-band transform for low-power speech applications
EURASIP Journal on Applied Signal Processing
VLSI Architecture for the Low-Computation Cycle and Power-Efficient Recursive DFT/IDFT Design
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Boolean circuit programming: A new paradigm to design parallel algorithms
Journal of Discrete Algorithms
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Many parallel Fast Fourier Transform (FFT) algorithms adopt multiple stages architecture to increase performance. However, data permutation between stages consumes volume memory and processing time. One FFT array processing mapping algorithm is proposed in this paper to overcome this demerit. In this algorithm, arbitrary 2k butterfly units (BUs) could be scheduled to work in parallel on n = 2s data (k = 0,1,..., s - 1). Because no inter stage data transfer is required, memory consumption and system latency are both greatly reduced. Moreover, with the increasing of BUs, not only does throughput increase linearly, system latency also decreases linearly. This array processing orientated architecture provides flexible tradeoff between hardware cost and system performance. In theory, the system latency is (s×2s-k) × tclk and the throughput is n/(s × 2s-k × tclk), where tclk is the system clock period. Based on this mapping algorithm, several 18-bit word-length 1024-point FFT processors implemented with TSMC0.18 μm CMOS technology are given to demonstrate its scalability and high performance. The core area of 4-BU design is 2.991 × 1.121 mm2 and clock frequency is 326 MHz in typical condition (1.8 V, 25°C). This processor completes 1024 FFT calculation in 7.839 μs.