Partial Order Reduction for Detecting Safety and Timing Failures of Timed Circuits

Authors:
Denduang Pradubsuwun;Tomohiro Yoneda;Chris Myers
Affiliations:
The author is with Tokyo Institute of Technology, Tokyo, 152--8552 Japan.,;The author is with National Institute of Informatics, Tokyo, 101--8430 Japan. E-mail: yoneda@nii.ac.jp,;The author is with the Department of Electrical and Computer Engineering, University of Utah, Salt Lake City, UT, USA.
Venue:
IEICE - Transactions on Information and Systems
Year:
2005

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Abstract

This paper proposes a partial order reduction algorithm for timed trace theoretic verification in order to detect both safety failures and timing failures of timed circuits efficiently. This algorithm is based on the framework of timed trace theoretic verification according to the original untimed trace theory. Consequently, its conformance checking supports hierarchical structure when verifying timed circuits. Experimenting with the STARI and DME circuits, the proposed approach shows its effectiveness.