Evaluation of Asymmetric TDD Systems Employing AMC and HARQ by Considering MCS Selection Errors

  • Authors:
  • Nandar Lynn;Osamu Takyu;Riaz Esmailzadeh;Masao Nakagawa

  • Affiliations:
  • The authors are with the Department of Information and Computer Science, Keio University, Yokohama-shi, 223-8522 Japan. E-mail: nandar@nkgw.ics.keio.ac.jp;The authors are with the Department of Information and Computer Science, Keio University, Yokohama-shi, 223-8522 Japan. E-mail: nandar@nkgw.ics.keio.ac.jp;The authors are with the Department of Information and Computer Science, Keio University, Yokohama-shi, 223-8522 Japan. E-mail: nandar@nkgw.ics.keio.ac.jp;The authors are with the Department of Information and Computer Science, Keio University, Yokohama-shi, 223-8522 Japan. E-mail: nandar@nkgw.ics.keio.ac.jp

  • Venue:
  • IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
  • Year:
  • 2006

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Abstract

In this paper, we evaluate the performance of asymmetric Time Division Duplex (TDD) system that employs Adaptive Modulation and Coding (AMC) and Hybrid ARQ, with consideration of the effect of control delays in TDD. Channel reciprocity characteristic in TDD allows utilization of open loop channel estimation to choose appropriate modulation and coding scheme (MCS) level for AMC. However, control delay in AMC and HARQ depends on TDD time slot allocation formats. Large control delay in AMC will result in false MCS selection due to the poor channel correlation between measured channel state from the received signals and instantaneous channel state of actual transmission with the MCS selected based on the measured channel state. We present an analytical approach to calculate the probability of MCS level selection error in different channel conditions for different asymmetric time slot allocations. From the theoretical and simulation results, it is shown that the instantaneous throughput per slot depends not only on maximum Doppler frequency but also on asymmetric slot allocations. Average delay time that yields error free packet reception in the downlink increases as the number of continuous downlink slots increases.