A 50% Power Reduction in H.264/AVC HDTV Video Decoder LSI by Dynamic Voltage Scaling in Elastic Pipeline

Authors:
Kentaro Kawakami;Jun Takemura;Mitsuhiko Kuroda;Hiroshi Kawaguchi;Masahiko Yoshimoto
Affiliations:
The author is with the Graduate School of Science and Technology, Kobe University, Kobe-shi, 657-8501 Japan. E-mail: kawakami@cs28.cs.kobe-u.ac.jp,;The author is with the Graduate School of Natural Science and Technology, Kanazawa University, Kanazawa-shi, 920-1192 Japan.,;The authors are with the Department of Computer and Systems Engineering, Kobe University, Kobe-shi, 657-8501 Japan.;The authors are with the Department of Computer and Systems Engineering, Kobe University, Kobe-shi, 657-8501 Japan.;The authors are with the Department of Computer and Systems Engineering, Kobe University, Kobe-shi, 657-8501 Japan.
Venue:
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Year:
2006

Citing 0
Cited 1

Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks

NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip

Quantified Score

Hi-index	0.00

Visualization

Abstract

We propose an elastic pipeline that can apply dynamic voltage scaling (DVS) to hardwired logic circuits. In order to demonstrate its feasibility, a hardwired H.264/AVC HDTV decoder is designed as a real-time application. An entropy decoding process is divided into context-based adaptive binary arithmetic coding (CABAC) and syntax element decoding (SED), which has advantages of smoothing workload for CABAC and keeping efficiency of the elastic pipeline. An operating frequency and supply voltage are dynamically modulated every slot depending on workload of H.264 decoding to minimize power. We optimize the number of slots per frame to enhance power reduction. The proposed decoder achieves a power reduction of 50% in a 90-nm process technology, compared to the conventional clock-gating scheme.