Theoretical Computer Science
UPPAAL—a tool suite for automatic verification of real-time systems
Proceedings of the DIMACS/SYCON workshop on Hybrid systems III : verification and control: verification and control
Verification of real-time designs: combining scheduling theory with automatic formal verification
ESEC/FSE-7 Proceedings of the 7th European software engineering conference held jointly with the 7th ACM SIGSOFT international symposium on Foundations of software engineering
Some Progress in the Symbolic Verification of Timed Automata
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Verification of the Fast Reservation Protocol with Delayed Transmission using the Tool Kronos
RTAS '98 Proceedings of the Fourth IEEE Real-Time Technology and Applications Symposium
Two examples of verification of multirate timed automata with Kronos
RTSS '95 Proceedings of the 16th IEEE Real-Time Systems Symposium
Proceedings of the 26th International Conference on Software Engineering
Issues in distributed timed model checking: Building Zeus
International Journal on Software Tools for Technology Transfer (STTT) - Special section on parallel and distributed model checking
A Scenario-Matching Approach to the Description and Model Checking of Real-Time Properties
IEEE Transactions on Software Engineering
Dealing with practical limitations of distributed timed model checking for timed automata
Formal Methods in System Design
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In this work we present an Eclipse plug-in for the VINTIME (Verifier of INtegrated TImed ModEls) suite of tools that combines high-level expressive power, unassisted property-preserving model reduction and distributed model checking to describe and verify complex real-time system designs and their properties.