Not all Delay Tests Are the Same - SDQL Model Shows True-Time

Authors:
Anis Uzzaman;Mick Tegethoff;Bibo Li;Kevin Mc Cauley;Shuji Hamada;Yasuo Sato
Affiliations:
Cadence Design Systems, Inc. Endicott, New York, USA;Cadence Design Systems, Inc. Endicott, New York, USA;Cadence Design Systems, Inc. Endicott, New York, USA;Cadence Design Systems, Inc. Endicott, New York, USA;Semiconductor Technology Academic Research Center (STARC), Yokohama, Japan;Semiconductor Technology Academic Research Center (STARC), Yokohama, Japan
Venue:
ATS '06 Proceedings of the 15th Asian Test Symposium
Year:
2006

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Estimation of delay test quality and its application to test generation

Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design

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Abstract

Assessing the effectiveness of transition fault testing by the test coverage is misleading and can result on lower product quality. In reality, the actual timing of the test for each fault determines if a delay defect of a given size is detected or not. Transition tests that use actual circuit timings to create tests with the tightest possible timing detect more defects and have higher test effectiveness for a given test coverage. This paper validates this assertion using a Statistical Delay Quality Model (SDQM) model to estimate the Statistical Delay Quality Level (SDQL) of several chips. The comparison includes transition tests generated with and without actual circuit timing as a function of the actual timing of the tests for each fault.