Testing Hierarchical Network-on-Chip Systems with Hard Cores Using Bandwidth Matching and On-Chip Variable Clocking

  • Authors:

  • Chunsheng Liu

  • Affiliations:

  • University of Nebraska-Lincoln, Omaha, NE 68182, USA

  • Venue:
  • ATS '06 Proceedings of the 15th Asian Test Symposium
  • Year:
  • 2006

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Abstract

In this paper, we present a testing scheme for hierarchical Network-on-a-Chip (NoC) system consisting of hard embedded cores using bandwidth matching. We show how bandwidth matching and on-chip clocking techniques can be used in NoC to adapt the hard cores to the network channel width. We use a cost function to represent the tradeoff between test time and area overhead. In case of a hierarchical architecture, we show that various configurations of a core can be modelled as a set of rectangles and rectangle packing can be used for optimized TAM design. Experimental results show that the proposed method can significantly reduce the overall cost.