High-Efficiency and Low-Power Architectures for 2-D DCT and IDCT Based on CORDIC Rotation

Authors:
Tze-Yun Sung;Yaw-Shih Shieh;Chun-Wang Yu;Hsi-Chin Hsin
Affiliations:
Chung Hua University, Taiwan;Chung Hua University, Taiwan;Chung Hua University, Taiwan;National Formosa University, Taiwan
Venue:
PDCAT '06 Proceedings of the Seventh International Conference on Parallel and Distributed Computing, Applications and Technologies
Year:
2006

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Abstract

Two dimensional discrete cosine transform (DCT) and inverse DCT (IDCT) have been widely used in many image processing systems. In this paper, efficient architectures with parallel and pipelined structures are proposed to implement 8脳 8 DCT and IDCT processors. In which, two 8-point DCT/IDCT processors with dual-bank of SRAM (128 words) and coefficient ROM (6 words), two multiplexers, and control unit are involved. The kernel arithmetic unit (AU) is designed by using CORDIC arithmetic. The proposed architectures for 2-D DCT/IDCT processors not only simplify hardware but also reduce the power consumption with high performances.