High-throughput sketch update on a low-power stream processor
Proceedings of the 2006 ACM/IEEE symposium on Architecture for networking and communications systems
Performance evaluation of highly efficient techniques for software implementation of LFSR
Computers and Electrical Engineering
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Stream processing architectures have been proposed as efficient and flexible platforms for network packet processing. As part of an investigation into stream-based network processors, we have implementedMMH, a family of almostuniversal hash functions for message authentication, on a SIMD stream processor (Imagine). The hash computation over an entire packet is a good fit for the stream programming model, with an abundance of producer-consumer locality: hash values are computed and stored in the stream register file (SRF), then used for calculating new hash values repeatedly. By using eight VLIW clusters, the construction is performed in a Multi-SIMDfashion, achieving multi- Gigabit-per-second throughput with a collision probability on the order of 2^-120 .