Dependability, power, and performance trade-off on a multicore processor
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
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A single-chip fail-safe microprocessor has been developed. It contains two processor cores and realizes self-checking feature by comparing the processing results of the two processor cores. In order to overcome redundant input disagreement problem, two mechanisms have been implemented. The one is input data exchange mechanism used with bus comparison feature. The other is memory data comparison and copy mechanism. With the memory data comparison mechanism, input data comparison overhead can be reduced, which is especially useful for short period control task with many input data. The microprocessor utilizes 0.18ìm CMOS process and integrates 512KB RAM and 25M transistors random logic in a 14.75mm x 14.75mm die. With the developed microprocessor, the size of a fault-tolerant controller can be reduced, which makes it easy to embed fault-tolerant controllers into equipments controlled.