User-Level Fine-Grained Adaptive Real-Time Scheduling via Temporal Reflection

Authors:
Sergio Ruocco
Affiliations:
National ICT Australia/ University of New South Wales, Australia
Venue:
RTSS '06 Proceedings of the 27th IEEE International Real-Time Systems Symposium
Year:
2006

Citing 0
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Abstract

Modern FPGA devices, which include (multiple) processor core(s) as diffused IP on the silicon die, provide an excellent platform for developing custom multiprocessor systems-on-programmable chip (MPSoPC) architectures. As researchers are investigating ...