The design of the UNIX operating system
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SOSP '89 Proceedings of the twelfth ACM symposium on Operating systems principles
Experimental comparison of memory management policies for NUMA multiprocessors
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Page placement algorithms for large real-indexed caches
ACM Transactions on Computer Systems (TOCS)
Exploring the design space for a shared-cache multiprocessor
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Reducing cache misses using hardware and software page placement
ICS '99 Proceedings of the 13th international conference on Supercomputing
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Space/time trade-offs in hash coding with allowable errors
Communications of the ACM
An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches
Proceedings of the 10th international conference on Architectural support for programming languages and operating systems
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HPCA '96 Proceedings of the 2nd IEEE Symposium on High-Performance Computer Architecture
CQoS: a framework for enabling QoS in shared caches of CMP platforms
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Organizing the Last Line of Defense before Hitting the Memory Wall for CMPs
HPCA '04 Proceedings of the 10th International Symposium on High Performance Computer Architecture
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IBM Journal of Research and Development - POWER5 and packaging
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Virtual hierarchies to support server consolidation
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A novel migration-based NUCA design for chip multiprocessors
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ACM: An Efficient Approach for Managing Shared Caches in Chip Multiprocessors
HiPEAC '09 Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers
RapidMRC: approximating L2 miss rate curves on commodity systems for online optimizations
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A case for bufferless routing in on-chip networks
Proceedings of the 36th annual international symposium on Computer architecture
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SCARAB: a single cycle adaptive routing and bufferless network
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Addressing shared resource contention in multicore processors via scheduling
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Micro-pages: increasing DRAM efficiency with locality-aware data placement
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Journal of Systems Architecture: the EUROMICRO Journal
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Dynamically managed multithreaded reconfigurable architectures for chip multiprocessors
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Handling the problems and opportunities posed by multiple on-chip memory controllers
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Reinventing scheduling for multicore systems
HotOS'09 Proceedings of the 12th conference on Hot topics in operating systems
Hardware execution throttling for multi-core resource management
USENIX'09 Proceedings of the 2009 conference on USENIX Annual technical conference
Contention-Aware Scheduling on Multicore Systems
ACM Transactions on Computer Systems (TOCS)
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Simple but Effective Heterogeneous Main Memory with On-Chip Memory Controller Support
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Online cache modeling for commodity multicore processors
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Controlling cache utilization of HPC applications
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A case for globally shared-medium on-chip interconnect
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FACT: a framework for adaptive contention-aware thread migrations
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Page coloring synchronization for improving cache performance in virtualization environment
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Jigsaw: scalable software-defined caches
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The Journal of Supercomputing
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This paper presents and studies a distributed L2 cache management approach through OS-level page allocation for future many-core processors. L2 cache management is a crucial multicore processor design aspect to overcome non-uniform cache access latency for good program performance and to reduce on-chip network traffic and related power consumption. Unlike previously studied hardwarebased private and shared cache designs implementing a "fixed" caching policy, the proposed OS-microarchitecture approach is flexible; it can easily implement a wide spectrum of L2 caching policies without complex hardware support. Furthermore, our approach can provide differentiated execution environment to running programs by dynamically controlling data placement and cache sharing degrees. We discuss key design issues of the proposed approach and present preliminary experimental results showing the promise of our approach.