Algorithms for Image Component Labeling on SIMD Mesh-Connected Computers
IEEE Transactions on Computers
Sequential Operations in Digital Picture Processing
Journal of the ACM (JACM)
Connectivity in Digital Pictures
Journal of the ACM (JACM)
On shrinking binary picture patterns
Communications of the ACM
Processor Arrays: Architecture and Applications
Processor Arrays: Architecture and Applications
Parallel Architectures and Algorithms for Image Component Labeling
IEEE Transactions on Pattern Analysis and Machine Intelligence
Parallel Image Component Labeling With Watershed Transformation
IEEE Transactions on Pattern Analysis and Machine Intelligence
A duality theorem for two connectivity-preserving parallel shrinking transformations
Future Generation Computer Systems - Cellular automata CA 2000 and ACRI 2000
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A new parallel algorithm is proposed for fat image labeling using local operators on image pixels. The algorithm can be implemented on an n*n mesh-connected computer such that, for any integer k in the range (1, log (2n)), the algorithm requires Theta (kn/sup 1/k/) bits of local memory per processor and takes Theta (kn) time. Bit-serial processors and communication links can be used without affecting the asymptotic time complexity of the algorithm. The time complexity of the algorithm has very small leading constant factors, which makes it superior to previous mesh computer labeling algorithms for most practical image sizes (e.g. up to 4096*4096 images). Furthermore, the algorithm is based on using stacks that can be realized using very fast shift registers within each processing element.